xilinx - VHDL - unconnected components in top module -

xilinx - VHDL - unconnected components in top module -

i working on project , i'm failing connect components in top module. can't see i'm doing wrong. suggestions highly appreciated.

besides not beingness able see components in rtl schematic, warnings:

warning:xst:1290 - hierarchical block <u0> unconnected in block <top>. removed design. warning:xst:1290 - hierarchical block <u1> unconnected in block <top>. removed design. warning:xst:2677 - node <u1/calc_deb> of sequential type unconnected in block <top>. warning:xst:2677 - node <u1/flipflops_1> of sequential type unconnected in block <top>. warning:xst:2677 - node <u1/flipflops_0> of sequential type unconnected in block <top>.

so here implementation of top module:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.std_logic_arith.all; utilize ieee.std_logic_unsigned.all; entity top port( calc: in std_logic; op: in std_logic_vector(1 downto 0); invalue: in std_logic_vector(3 downto 0); clk: in std_logic ); end top; architecture behavioral of top component alu port( op : in std_logic_vector(1 downto 0); invalue : in std_logic_vector(3 downto 0); regvalue : in std_logic_vector(3 downto 0); result: out std_logic_vector(4 downto 0); clk : in std_logic ); end component; component debouncer port( calc : in std_logic; calc_deb : out std_logic; clk: in std_logic ); end component; signal calc_debaux: std_logic; signal regvalueaux: std_logic_vector(3 downto 0); signal resultaux: std_logic_vector(4 downto 0); --signal op: std_logic_vector(1 downto 0); --signal op: std_logic_vector(3 downto 0); begin u0: alu port map(op => op, invalue=>invalue, regvalue=>regvalueaux, result=>resultaux, clk=>clk); u1: debouncer port map(calc=>calc, alc_deb=>calc_debaux, clk=>clk); end behavioral;

and here 2 entities i'm instantiating in top module:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.std_logic_arith.all; utilize ieee.std_logic_unsigned.all; entity alu port ( op : in std_logic_vector(1 downto 0); invalue : in std_logic_vector(3 downto 0); regvalue : in std_logic_vector(3 downto 0); result: out std_logic_vector(4 downto 0); clk : in std_logic ); end alu; architecture archi of alu signal res_temp: std_logic_vector(4 downto 0); signal aux1, aux2: std_logic_vector(4 downto 0); begin aux1 <= ('0' & invalue); aux2 <= ('0' & regvalue); result <= res_temp; process (invalue, op) begin case op when "00" => res_temp <= (aux1) + (aux2) ; when "01" => res_temp <= aux1 - aux2; when "10" => res_temp <= (invalue , regvalue); when others => res_temp <= '0' & (regvalue(0) & regvalue(3 downto 1)); end case; end process; end archi ; library ieee; utilize ieee.std_logic_1164.all; utilize ieee.std_logic_arith.all; utilize ieee.std_logic_unsigned.all; entity debouncer port ( calc : in std_logic; calc_deb : out std_logic; clk: in std_logic); end debouncer; architecture behavioral of debouncer signal flipflops : std_logic_vector(1 downto 0); --input flip flops signal counter_set : std_logic; --sync reset 0 signal counter_out : std_logic_vector(8 downto 0) := (others => '0'); --counter output begin counter_set <= flipflops(0) xor flipflops(1); --determine when start/reset counter process(clk) begin if(clk'event , clk = '1') flipflops(0) <= calc; flipflops(1) <= flipflops(0); if(counter_set = '1') --reset counter because input changing counter_out <= (others => '0'); elsif(counter_out(8) = '0') --stable input time not yet met counter_out <= counter_out + 1; else --stable input time met calc_deb <= flipflops(1); end if; end if; end process; end behavioral;

i more warnings:

synthesizing unit <top>. related source file "d:/mestrado/1o ano/1o semestre/psd/projectos/andgates/top.vhd". warning:xst:646 - signal <resultaux> assigned never used. unconnected signal trimmed during optimization process. warning:xst:653 - signal <regvalueaux> used never assigned. sourceless signal automatically connected value 0000. warning:xst:646 - signal <calc_debaux> assigned never used. unconnected signal trimmed during optimization process. unit <top> synthesized.

i have spend huge time in (this part of bigger project, i'm trying restart going piece piece facilitate troubleshooting) , clueless. :(

thank time.

your top level entity, top, not seem have output pins. ise pretty smart when comes trying save fpga resources during synthesis. logic not used somehow determine state of output pin in top level entity synthesised away. i'm guessing thinks entire design (for lack of improve word) useless none of used drive output pin of top.

try connecting resultaux and/or calc_debaux output signals output ports of top itself. clears warnings.

vhdl xilinx xilinx-ise