testing - How to write a verilog testbench to loop through 4 inputs? -

testing - How to write a verilog testbench to loop through 4 inputs? -

i have create verilog code , testbench schematic.

i have design here.

module prob1(input wire a,b,c,d, output wire out); assign out = (a||d)&&(!d&&b&&c); endmodule

here have testbench far.

module prob1_tb(); reg a,b,c,d; wire out; prob1 prob1_test(a,b,c,d, out); initial begin for(i=0; i=16; i=i+1) <loop code here> end end endmodule

now guess part having issue how can convert number 4 inputs beingness used in schematic. or there improve way go doing this?

here simple way using concatenation operator:

module prob1(input wire a,b,c,d, output wire out); assign out = (a||d)&&(!d&&b&&c); endmodule module prob1_tb(); reg a,b,c,d; wire out; prob1 prob1_test(a,b,c,d, out); initial begin $monitor(a,b,c,d,out); (int i=0; i<16; i=i+1) begin {a,b,c,d} = i; #1; end end endmodule /* output: 00000 00010 00100 00110 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11101 11110 */

yes, there improve ways verify logic. first thing introduce random values (refer $urandom functions in ieee std 1800-2009). of course, need perform checks of output using model, in case trivial.

depending on how much time (and training) have, adopt standard flow, such universal verification methodology (uvm). people build careers around verification.

loops testing verilog