fpga - Is there a way to sum multi-dimensional arrays in verilog? -

fpga - Is there a way to sum multi-dimensional arrays in verilog? -

this think should doable, failing @ how in hdl world. have design inherited summing multidimensional array, have pre-write add-on block because 1 of dimensions synthesize-time option, , cater add-on that.

if have reg tap_out[src][dst][tap], src , dst set 4 , tap can between 0 , 15 (16 possibilities), want able assign output[dst] sum of tap_out particular dst.

right our addition block takes combinations of tap_out each src , tap , sums them in pairs each dst: tap_out[0][dst][0] tap_out[1][dst][0] tap_out[2][dst][0] tap_out[3][dst][0] tap_out[0][dst][1] .... tap_out[3][dst][15]

is there way improve in verilog? in c utilize for-loops, doesn't seem possible here.

for-loops work fine in situation

integer src_idx, tap_idx; @* begin sum = 0; (scr_idx=0; src_idx<4; src_idx=scr_idx+1) begin (tap_idx=0; tap_idx<16; tap_idx=tap_idx+1) begin sum = sum + tap_out[src_idx][dst][tap_idx]; end end end

it unroll big combinational logic during synthesis , results should same adding bits line line.

propagation delay big summing logic have timing issue. synthesizer should find optimum timing/area when told clocking constraint. if logic complex synthesizer, add together own partial sum logic can run in parallel

reg [`widht-1:0] /*keep*/ partial_sum [3:0]; // tell synthesis preserve these nets integer src_idx, tap_idx; @* begin sum = 0; (scr_idx=0; src_idx<4; src_idx=scr_idx+1) begin partial_sum[scr_idx] = 0; // partial sums independent of each other can run in parallel (tap_idx=0; tap_idx<16; tap_idx=tap_idx+1) begin partial_sum[scr_idx] = partial_sum[scr_idx] + tap_out[src_idx][dst][tap_idx]; end sum = sum + partial_sum[scr_idx]; // sum partial sums end end

if timing still issue, have must treat logic multi-cycle , sample value clock cycles after input changed.

verilog fpga hdl