make - Makefile conditional not respecting target-specific variables -



make - Makefile conditional not respecting target-specific variables -

is there way utilize native makefile if-else conditional , have respects target-specific variables re-assignments?

example makefile:

#!/usr/bin/make config = debug .phony: test printme test: override config=release test: printme @echo "done." printme: ifeq "$(config)" "debug" @echo "should debug -> $(config)" else @echo "should release -> $(config)" endif

running make test prints next output:

should debug -> release done.

the output i'm looking should release -> release how can accomplish that? need utilize shell conditionals instead?

this behavior seems logical me: @ time of parsing makefile, config defined debug. ifeq conditional uses value of config knows @ time. hence chooses ifeq branch outputs "should debug".

the target-specific variable defined release target test. prerequisite printme knows target-specific variable , ouputs release.

may suggest set variable make on command line purpose want. it's not many more characters write when invoking make brings seem willing.

make config=release

makefile make

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